1. Field of the Invention
This application relates to the field of high density interconnect systems, and more particularly, to the field of computerized layout of conductor patterns for high density interconnect systems.
2. Background Information
A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a microcomputer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inch long by 2 inch wide by 0.050 inch thick. Even more important, this interconnect structure can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where as many as 50 chips having a cost of as much as $2,000.00 each, may be incorporated in a single system on one substrate. This repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1989, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, entitled "Method and Configuration for Testing Electronic Circuit and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application Ser. No. 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; and U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications is incorporated herein by reference.
Briefly, in this high density interconnect structure, a ceramic substrate (such as alumina) is provided which may be 50 to 100 mils thick and of appropriate size and strength for the overall system. This size is typically less than 2 inches square. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This is done by starting with a bare substrate having a uniform thickness and the desired size. Laser milling is then used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the substrate surrounding the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to the softening point of the ULTEM.RTM. polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C.) depending on the formulation used and then cooled to thermoplastically bond the individual components to the cavity. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E. I. du Pont de Nemours Company, which is .apprxeq.0.0005-0.003 inch (.apprxeq.12.5-75 microns) thick is pre-treated to promote adhesion and coated on one side with the ULTEM.RTM. polyetherimide resin or another thermoplastic and laminated across the top of the chips, other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are laser drilled in the Kapton.RTM. and ULTEM.RTM. layers in alignment with contact pads on the electronic components to which it is desired to make contact. A metallization layer is deposited over the Kapton.RTM. layer. This metallization extends into the via holes and makes electrical contact to contact pads disposed thereunder. This metallization layer may be patterned in the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process.
Additional dielectric and metallization layers are provided as required in order to provide the desired interconnection pattern. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of the related U.S. Pat. No. 4,835,704.
In this manner, the entire interconnect structure can be fabricated from start to finish (after definition of the required conductor patterns and receipt of the electronic components) in as little as .apprxeq.8-12 hours.
This high density interconnect structure provides many advantages. Included among these are the fact that it results in the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require the prepackaging of each semiconductor chip, the design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities may be formed in an already fired ceramic substrate by laser milling. This milling process is straightforward and fairly rapid with the result that once a desired configuration for the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips in as little as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once that interconnect structure has been defined, assembly of the system on the substrate may begin. First, the chips are mounted on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in one day and in the event of a high priority rush, could be completed in four hours. Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than required with other packaging techniques.
As systems being assembled in the HDI format increase in complexity, the difficulty and the computer time required to design an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate increases disproportionately. The increasing complexity can result in a need to add additional conductor layers to the high density interconnect structure in order to complete routing of all interconnections. Such additional layers complicate the fabrication process and increase the cost of the final system and the time required to produce it. A major cost is the time required for so-called rip-up passes in the routing program.
A rip-up pass is a routing pass used by the routing program when the routing program has been unable to complete all of the interconnections using constructive passes. This inability to complete all interconnections may be because of excessive interconnection density or excessive conductor congestion in parts of the routing surface. During a rip-up pass the areas in the routing plane where high congestion caused an inability to complete all routes are assigned high importance, weight or value within the router's route selection system which selects the lowest-weight successful route for a conductor. The system then removes some or all of the interconnections fixed during that previous pass and begins routing the unconnected connections. The high weight assigned to the previously heavily congested areas causes the router to route as much wiring as possible away from these high value areas. Where a second routing pass is also unsuccessful, additional values are assigned in accordance with the areas of congestion and failed routing in that second pass and a third routing pass is undertaken. Eventually, a complete successful routing of the circuit is obtained or the problem of routing a few remaining unrouted conductors is assigned to an engineer or an additional conductor layer is added to the interconnection pattern being routed to relieve congestion and provide more routes that the router can use in interconnecting the components.
Further, even in the event that the routing program is finally successful in routing all of the conductors in the desired number of layers, substantial time may be consumed in the routing process.
In a high density interconnect system of the general type discussed above, the pattern of each metallization layer and the via holes in each dielectric layer must either be individually tailored to the exact positions of the various integrated circuit chips (as placed) or an adaptive lithography system must adjust an ideal metallization and via hole pattern in accordance with the actual position of the various integrated circuit chips. In the above-identified related U.S. Pat. No. 4,835,704, this problem is solved by adaptation of an ideal metallization pattern in accordance with the actual locations of the integrated circuits chips and their contact pads by modifying the metallization pattern to properly connect to the contact pads. That adaptation is enabled by providing a "picture frame" around the allowed location of each integrated circuit chip in which adaptation of the metal layer takes place. In order to facilitate that adaptation, one of the design rules for the ideal metallization is that each metal path which crosses the picture frame must do so perpendicular to those edges of the picture frame which it crosses. The ideal metallization pattern over the chip is maintained with respect to the chip and thus, must be shifted and/or rotated with respect to the portion outside the picture frame in accordance with any shift and/or rotation of the chip with respect to its ideal location. The ideal metallization pattern beyond the outer edge of the picture frame is maintained with respect to the substrate, i.e. unchanged during the adaptation process. Adaptation to the actual chip location is accomplished by modifying the metallization pattern within the picture frame area to properly connect from the ideal metallization pattern at the outside edge of the picture frame to the shifted/rotated ideal metallization pattern over the chip. This results in the angling of conductors in the picture frame area where the chip is displaced perpendicular to, or rotated with respect to the ideal position of those connections.
Typically, hybrid routing programs enable the user to define the first layer of metal as having a preferred direction of conductor travel and the second layer of metal as having the perpendicular direction as the preferred direction of travel. Most routing programs also enable the user to make these preferences requirements. These preferences or requirements apply to the entire conductor layer. Consequently, the requirement that conductors cross the picture frame perpendicular to the picture frame edge they are crossing can be accommodated with such routing programs by requiring that the first metallization layer run in one orientation, say horizontally, and the second routing layer run in a perpendicular orientation, say vertical. We have found that one of the causes of routing congestion and the failure to complete interconnections with the Omnicards program is a result of requiring one layer of conductors to run horizontally only and the other layer of conductors to run vertically only, both horizontal and vertical being in the sense of a layout diagram on a piece of paper and not with respect to a physical orientation in which vertical might imply perpendicular to the surface of the substrate or electronic components.
In adapting the "Omnicards" hybrid circuit layout program available from Task Technologies, Inc. of Rochester, N.Y. to handle the original routing of the metal conductors in the ideal metallization pattern, we have found that the requirement that all wires cross the picture frame perpendicular to the edges thereof substantially complicates the routing process for the software, and in many cases, results in a failure to connect all modes as is required. The above-identified related application Ser. No. 361,623 solves this adaptation problem for those situations where the components can be placed with sufficient accuracy, by providing enlarged contact islands in the first layer of the ideal metallization pattern which are aligned with the ideal positions of associated contact pads on the electronic components, most of which are integrated circuit chips. So long as the components are placed with sufficient accuracy that the contact island in the first layer of the ideal metallization pattern will overlap the contact pad on the component by the amount required for an interconnecting via, no adaptation of the metallization pattern is required. Instead, the via in the dielectric layer is placed where its bottom is entirely over the contact pad and where the contact island in the first metallization layer will fully overlap it.
Use of this technique of including contact islands in the first layer of metallization eliminates the need for a picture frame area and thereby substantially simplifies the routing process as executed by the Omnicards program. Since typical pad dimensions and spacings for integrated circuit chips are 4 mils (100 microns) square, pads located on 8 mil (200 microns) centers and conductive runs in the HDI system are typically 1 mil (25 microns) wide, contact islands 2.4 mils (0.06 mm) square allow sufficient clearance for conductors to pass between adjacent contact islands designed to align with integrated circuit contact pads and will accommodate placement errors of up to about .+-.2 mils. Present manufacturing tolerances are not sufficiently tight to enable this contact island technique to be used with systems containing a significant number of chips.
Accordingly, there is a need for an improved routing technique which more easily accommodates the "picture frame" requirements for high density interconnect structures.